1. Field of the Invention
The invention relates to a memory device and a method of fabricating the same, and particularly to a memory device having a vertical cell and a method of fabricating the same.
2. Description of Related Art
Memories are semiconductor devices used for storing information or data. With the development of powerful microprocessors, the software is capable of programming and calculating increasing amount of data. Thus, the demand for the capacity of memories increases. In various memory products, non-volatile memories allow multiple times of data programming, reading, and erasing. The data stored therein are retained even after power to the memories is turned off In light of the aforementioned advantages, non-volatile memories have become one of the most widely-adopted memories in personal computers and other electronic equipments.
The electrically erasable programmable read only memories (EEPROMs) in non-volatile memories possess the ability to store, read and erase data for multiple times. Moreover, the EEPROMs have the advantage of not losing the stored data even after power of the system has been turned off. Therefore, the EEPROMs are widely used in the personal computers and electronic equipments. Typical EEPROMs fabricate floating gates and control gates from doped polysilicon. When the memory is being programmed, the electrons implanted into the floating gate are uniformly distributed in an entire polysilicon floating gate layer. However, if the tunnel oxide layer under the polysilicon floating gate layer has defects, it can easily cause a leakage current in the device, thereby affecting the reliability of the device.
Therefore, in order to solve the issue of current leakage in the EEPROM device, a conventional method utilizes stacked gate structures having a nonconductive charge storage layer to replace the polysilicon floating gate. Moreover, another advantage obtained from replacing the polysilicon floating gate with the charge storage layer is that the electrons are only locally stored in a neighboring portion of the channel region above the source region or the drain region while the device is programmed. Therefore, during the programming process, voltages can be respectively applied on the source region and the control gate at one end of the stacked gate structure. Furthermore, at the silicon nitride layer of the drain region near another end of the stacked gate structure, electrons are generated with a form of Gaussian distribution. Alternatively, voltages can be respectively applied on the drain region and the control gate of one end of the stacked gate structure. Moreover, at the silicon nitride layer of the source region near another end of the stacked gate structure, electrons are generated with a form of Gaussian distribution. In other words, by changing the voltages applied to the control gate and to either the source region or the drain region at the two sides, a single silicon nitride layer can have two storage regions that have electrons with a Gaussian distribution property, either one of the storage regions having electrons with the Gaussian distribution property, or none of the electrons stored in both storage regions. Hence, for this type of flash memory with the silicon nitride material replacing the floating gate, a single memory cell can be written with four different states. Therefore, this type of flash memory is considered a 2-bit-per-cell memory.
Conventionally, in order to increase the number of bits of a memory cell, a memory structure with a vertical memory cell is developed. This type of memory cell is a 4-bit-per-cell flash memory. However, between two vertically adjacent bits in the memory, the phenomenon of charge punch through happens easily. Hence, a severe leakage current in the memory structure is induced. In addition, the memory structure of the vertical cell further has problems such as asymmetric threshold voltages and asymmetric programming speeds, which consequently reduce the performance of the memory device having the vertical cell.
How to achieve a higher memory density while solving the problems aforementioned for the memory device to maintain device performance at a certain level is the most important issue to be solved.